1. Field of the Invention
The present invention relates to a memory module including at least one command-address signal register and a plurality of memory chips. Each of the memory chips has a command-address signal terminal with an active-termination circuit. The memory chips are divided into a plurality of memory groups of even-numbered ranks. The command-address signal register is connected to the plurality of memory chips through internal wiring. The present invention further relates to a memory system using the above-described memory module and particularly relates to a memory module that can reduce signal reflections in a stub with a T-branch structure and operate with high speed and a memory system using this memory module.
2. Description of the Related Art
FIG. 1 illustrates an example known memory module 1 including a command-address register (CAR) 3 and a plurality of dynamic random access memories (DRAM) 2 as memory chips. This drawing illustrates the topology of command-address (CA) wiring of the memory module 1. The DRAMs 2 of this memory module 1 are double-data-rate synchronous (DDR-S) DRAMs.
In the memory module 1, the DRAMs 2 are divided into two groups. One of the two groups includes four DRAMs 2 on one surface of a package substrate and four DRAMs 2 on the other surface thereof. The other of the two groups includes five DRAMs 2 on one surface of the package substrate and five DRAMs 2 on the other surface thereof. These two groups of DRAMs 2 and the CAR 3 are connected to each other through the CA wiring with a T-branch structure.
The above-described topology is provided for reducing the length of the CA wiring so as to reduce the area on which the CA wiring is provided. According to this configuration, however, the length of a stub increases. Subsequently, the time constant of signal reflections becomes large. Therefore waveforms obtained where a high-speed signal is transmitted through this wiring are significantly distorted by multiple reflections, as shown in FIG. 2.
The above-described known memory module has a problem that the waveforms thereof are significantly distorted due to a high-speed signal.
The problem is caused by the configuration of the memory module. That is to say, the DRAMs functioning as memory chips are divided into two groups and these two groups are connected to each other via the wiring with a T-branch structure. Since the length of the stub increases, the time constant of signal reflections increases and the distortion of waveforms becomes significant.
Such related technique is disclosed in, for example, Japanese Patent Application No. JP 2001-270518.